1. Field of Invention
This invention relates to integrated circuits, and in particular multiplying clock frequencies using digital techniques.
2. Description of Related Art
Most clock frequency multipliers use a phase locked loop (PLL) when a tightly controlled clock is required, or a simple delay chain when the clock is not critical. The PLL provides a stable and tightly controlled output, but is an analog circuit requiring an analog fabrication process using a large area on a chip. The PLL also has a tendency to dissipate a lot of power. Simple delay chains that can be implemented in digital logic and use relatively low power are prone to variations in period and frequency as a result of manufacturing process, or different operating environments, and are not suitable for timing critical designs.
In U.S. Pat. No. 4,339,722 (Sydor et al.) a digital frequency multiplier is described using counters where the number of internal clocks are counted within the period of an incoming signal and compared to the number of clocks counted in a second counter having N times the clock rate of the first counter. For this scheme to work an internal clock generator must be N times the clock driving the counter receiving the input signal which in turn must be faster than the incoming signal.
In U.S. Pat. No. 5,321,734 (Ogata) a frequency multiplier circuit is described where the output signal is blocked. The blocking occurs when the delay relationship of the output clock of double frequency is too far askew with respect to the master clock.
In U.S. Pat. No. 5,436,939 (Co et al.) a multiphase clock generator is described using a phase locked loop and having the capability of providing a multiple of clock signals shifted in phase from one another. These phase shifted waveforms are then combined to produce an output clock signal which is a frequency double of the input clock.
Referring to U.S. Pat. No. 5,530,387 (Kim), a frequency doubler circuit is described using delay circuits, a detector and a decoder to determine where in time a midpoint of a reference clock pulse occurs. This allows a clock signal of double frequency to be created at a particular duty cycle and controlled to be within an acceptable tolerance for different variations of process and environment. However, this circuit is not free of glitches caused by clock jitter.
In timing critical situations it is important to have a stable clock and to have all derivatives of that clock, such as double frequency clocks, to be stable throughout variations in the semiconductor process that created the circuitry and the environment that contains the circuitry. One way to produce a double frequency clock that maintains its relationship to a master clock is to create a design that adjusts the double frequency clock to be within an allowed phase relationship to the master clock. By continuously monitoring and adjusting when necessary, clocks of different frequencies can maintain a tight relationship that permits critical logic to operate.